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EUA6204
1.36-W Mono Fully Differential Audio Power Amplifier
DESCRIPTION
The EUA6204 is a mono fully-differential audio amplifier, capable of delivering 1.36W of continuous average power to an 8 BTL load with less than 1% distortion (THD+N) from a 5V power supply, and 720mW to a 8 load from a 3.6V power supply. The EUA6204 is ideal for PDA/smart phone application due to features such as -80-dB supply voltage rejection from 20Ha to 2kHz, improved RF rectification immunity, small 20mm2 PCB area, and a fast startup with minimal pop. The EUA6204 is available in a MSOP-8 and in the space-saving 3mm N 3mm DFN package.
FEATURES
Supply Voltage 2.5V to 5.5V 1.36W into 8 from a 5-V Supply at THD=1% (typ) Low Supply Current: 4mA typ at 5V Shutdown Current: 0.01A typ Fast Startup with Minimal Pop Only Three External Components - Improved PSRR (-80dB) for Direct Battery Operation - Full Differential Design Reduces RF Rectification - -63dB CMRR Eliminates Two Input Coupling Capacitors RoHS Compliant and 100% Lead (Pb)-Free
APPLICATIONS
Wireless Handsets PDAs Portable Devices
Typical Application Circuit
DS6204 Ver1.1
June. 2006
1
EUA6204
Block Diagram
Pin Configurations
Package Pin Configurations
DFN-8
MSOP-8
Pin Description
SYMBOL PIN DESCRIPTION
Shutdown Bypass IN+ INVO+ VDD GND VODS6204 Ver1.1 June. 2006
1 2 3 4 5 6 7 8
Shutdown terminal Mid-supply voltage, adding a bypass capacitor improves PSRR Positive differential input Negative differential input Positive BTL output Power supply High-current ground Negative BTL output
2
EUA6204
Ordering Information
Order Number EUA6204JIR1 EUA6204MIR1 Package Type DFN-8 MSOP-8 Marking xxxx A6204 xxxx A6204 Operating Temperature range -40C to 85C -40C to 85C
EUA6204
1/4
1/4
1/4
1/4
Lead Free Code 1: Lead Free 0: Lead Packing R: Tape & Reel Operating temperature range I: Industry Standard Package Type J: DFN M: MSOP
DS6204 Ver1.1
June. 2006
3
EUA6204
Absolute Maximum Ratings
u
Supply voltage, VDD
u
--------------------------------------------------------------------------------------------
6V
Input voltage, VI
u u
----------------------------------------------------------------------------
-0.3 V to VDD +0.3V -65C to 150C 2kV 150C
Storage temperature rang, Tstg ------------------------------------------------------------------ESD Susceptibility
u
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Junction Temperature
u
Thermal Resistance JC (MSOP) JA (MSOP) JA (DFN) ------------------------------------------------------------------------------------------56C/W ------------------------------------------------------------------------------------------- 160C/W --------------------------------------------------------------------------------------------- 50C/W
Recommended Operating Conditions
MIN NOM MAX UNIT
Supply Voltage, VDD High-level input voltage, VIH Low-level input voltage, VIL Operating free-air temperature, TA
2.5 1.55 -40
5.5 0.5 85
V V C
Electrical Characteristics, TA=25C Symbol
VOS
Parameter
Output offset voltage (measured differentially)
Conditions
VI=0V differential, Gain=1V/V, VDD=5.5V VDD=2.5V to 5.5V VDD=2.5V to 5.5V VDD=2.5V, VIC=0.5V to 1.7V VDD=5.5V, VIC=0.5V to 4.7V RL=8, VIN+=VDD, VIN+=0V, Gain=1V/V VIN-=0V or VIN-=VDD VDD=5.5V VDD=3.6V VDD=2.5V VDD=5.5V VDD=3.6V VDD=2.5V
Min
-9
EUA6204 Unit Typ Max.
2 -85 9 -60 VDD-0.8 -63 -63 0.45 0.37 0.26 4.95 3.18 2.13 58 3 4 0.01 -40 -40 mV dB V dB
PSRR Power supply rejection ratio VIC CMRR Common mode input range Common range mode rejection
0.5
Low-output swing
V 0.4 V 100 100 8 1 42k RI A A mA A V/V k
High-output swing |IIH| |IIL| IQ I(SD) High-level input current,
Shutdown
Gain=1V/V RL=8, VIN+=VDD, VIN-=0V or VIN-=VDD, VIN+=0V
2
VDD=5.5V, VI=5.8V VDD=5.5V, VI=-0.3V VDD=2.5V to 5.5V, no load V( Shutdown )0.5V, VDD=2.5V to 5.5V, RL= 8 RL= 8 38k RI
Low-level
input
current,
Shutdown
Quiescent current Supply current Gain Resistance from shutdown to GND
40k RI 100
DS6204 Ver1.1
June. 2006
4
EUA6204
Operating Characteristics, TA=25C, Gain=1V/V Symbol Parameter Conditions
VDD=5V THD+N=1%, f=1kHz,RL=8 VDD=3.6V VDD=2.5V VDD=5V THD+N=10%, f=1kHz,RL=8 VDD=3.6V VDD=2.5V VDD=5V, PO=1W, RL=8, f=1kHz VDD=3.6V, PO=0.5W, RL=8, f=1kHz VDD=2.5V, PO=200mW, RL=8, f=1kHz VDD=3.6V, f = 217Hz Inputs ac-grounded f=20Hz with Ci=2F, to 20kHz V(Ripple)=200mVpp VDD=5V, PO=1W, RL=8 No VDD=3.6V, f=20Hz to 20kHz, weighting Inputs ac-grounded with A Ci=2F weighting VDD=3.6V f=217Hz VIC=1Vpp 38 from VDD=3.6V, CBYPASS=0.1F
EUA6204 Unit Min Typ Max.
1.36 0.72 0.33 1.7 0.85 0.4 0.15 0.1 0.1 -77 -60 100 25 19 -64 40 27 44 VRMS dB dB W
PO
Output power
W
THD+N
Total harmonic distortion plus noise Supply ratio ripple rejection
%
KSVR SNR Vn
Signal-to-noise ratio Output voltage noise Common mode rejection ratio Feedback resistance Start-up shutdown time
CMRR RF
dB k ms
DS6204 Ver1.1
June. 2006
5
EUA6204
Typical Operating Characteristics
DS6204 Ver1.1
June. 2006
6
EUA6204
DS6204 Ver1.1
June. 2006
7
EUA6204
DS6204 Ver1.1
June. 2006
8
EUA6204
Application Information
Application Schematics Figure14 through Figure15 show application schematics for differential and single-ended inputs. Typical values are shown in Table1.
Table1. Typical Component Value Component RI C(BYPASS) CS CI Value 40k 0.22F 1F 0.22F
Power Dissipation Power dissipation is a major concern when designing a successful amplifier, whether the amplifier is bridged or single-ended. A direct consequence of the increased power delivered to the load by a bridge amplifier is an increase in internal power dissipation. Since the EUA6204 has two operational amplifiers in one package, the maximum internal power dissipation is 4 times that of a single-ended amplifier. The maximum power dissipation for a given application can be derived from the power dissipation graphs of from equation1.
PDMAX = 4 * (VDD ) 2 /(2 2 R L ) ------------(1)
It is critical that the maximum junction temperature TJMAX of 150C is not exceeded. TJMAX can be determine from the power derating curves by using PDMAX and the PC board foil area. By adding additional copper foil, the thermal resistance of the application can be reduced, resulting in higher PDMAX. Additional copper foil can be added to any of the leads connected to the EUA6204. If TJMAX still exceeds 150C, then additional changes must be made. These changes can include reduced supply voltage, higher load impedance, or reduced ambient temperature. Internal power dissipation is a function of output power. Proper Selection of External Components Gain-Setting Resistor Selection The input resistor (RI) can be selected to set the gain of the amplifier according to equation2. Gain=RF/RI (2)
The internal feedback resistors (RF) are trimmed to 40k. Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference voltage depends on matched ratios of the resistors. CMRR, PSRR, and the cancellation of the second harmonic distortion diminishes if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or better to keep the performance optimized. Bypass Capacitor (CBYPASS) and Start-up Time The internal voltage divider at the Bypass pin of this device sets a mid-supply voltage for internal references and sets the output common mode voltage to VDD/2. Adding a capacitor to this pin filters any noise into this pin and increases kSVR. C(BYPASS) also determines the rise time of VO+ and VO- when the device is taken out of shutdown. The larger the capacitor, the slower the rise time. Show the relationship of C(BYPASS) to start-up time as Figure10.
DS6204 Ver1.1
June. 2006
9
EUA6204
Input Capacitor (CI) The EUA6204 does not require input coupling capacitors if using a differential input source that is biased from 0.5V to VDD -0.8V. Use 1% tolerance or better gain-setting resistors if not using input coupling capacitors. In the single-ended input application an input capacitor, CI, is required to allow the amplifier to bias the input signal to the proper dc level. In this case, CI and RI form a high-pass filter with the corner frequency determined in equation3.
f C = 1 2 R C II
In this example, CI is 0.16F, so one would likely choose a value in the range of 0.22F to 0.47F. Ceramic capacitors should be used when possible, as they are the best choice in preventing leakage current. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications, as the dc level there is held at VDD/2, which is likely higher than the source dc level. It is important to confirm the capacitor polarity in the application. Decoupling Capacitor (CS) The EUA6204 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1F to 1 F, placed as close as possible to the device VDD lead works best. For filtering lower frequency noise signals, a 10-F or greater capacitor placed near the audio power amplifier also helps, but is not required in most applications because of the high PSRR of this device.
(3)
The value of CI is important to consider as it directly affects the bass (low frequency) performance of the circuit. Consider the example where RI is 10k and the specification calls for a flat bass response down to 100Hz. Equation 3 is reconfigured as equation4.
1 C= I 2 R f IC
(4)
DS6204 Ver1.1
June. 2006
10
EUA6204
Package Information
DFN-8
NOTE 1. All dimensions are in millimeters, is in degrees 2. M: The maximum allowable corner on the molded plastic body corner 3. Dimension D does not include mold protrusions or gate burrs. Mold protrusions and gate burrs shall not exceed 0.15mm per side 4. Dimension E does not include interterminal mold protrusions or terminal protrusions. Interminal mold protrusions and/or terminal protrusions shall not exceed 0.20mm per side 5. Dimension b applies to plated terminals. Dimension A1 is primarily Y terminal plating, but may or may not include a small protrusion of terminal below the bottom surface of the package 6. Burr shall not exceed 0.060mm 7. JEDEC MO-229 SYMBOLS A A1 A3 B D D1 E E1 e L aaa bbb ccc M MIN. 0.81 0 -----0.25 2.85 -----2.85 ----------0.25 ---------------------12 DIMENSIONS IN MILLIMETERS NOM. MAX. 0.9 1.00 0.015 0.03 0.20 REF -----0.30 0.37 3.00 BSC 3.15 2.3 BSC -----3.00 BSC 3.15 1.5 BSC -----0.65 BSC ----0.35 0.45 0.25 -----0.10 -----0.10 ----------0.05 -----0
DS6204 Ver1.1
June. 2006
11
EUA6204
MSOP-8
NOTE 1. Package body sizes exclude mold flash and gate burrs 2. Dimension L is measured in gage plane 3. Tolerance 0.10mm unless otherwise specified 4. Controlling dimension is millimeter. Converted inch dimensions are not necessarily exact. SYMBOLS A A1 A2 b C D E E1 e L y c DIMENSIONS IN MILLIMETERS MIN. NOM. MAX. 0.81 0.95 1.10 0.05 0.09 0.15 0.76 0.86 0.97 0.28 0.30 0.38 0.13 0.15 0.23 2.90 3.00 3.10 4.70 4.90 5.10 2.90 3.00 3.10 -----0.65 ----0.40 0.53 0.66 ----------0.10 0 -----6 DIMENSIONS IN INCHES MIN. NOM. MAX. 0.032 0.0375 0.043 0.002 0.004 0.006 0.030 0.034 0.038 0.011 0.012 0.015 0.005 0.006 0.009 0.114 0.118 0.122 0.185 0.193 0.201 0.114 0.118 0.122 -----0.026 -----0.016 0.021 0.026 ----------0.004 0 -----6
DS6204 Ver1.1
June. 2006
12

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